1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of fabricating a CMOS transistor.
2. Description of the Related Art
Demands for CMOS transistors with high density and high operating speed have required the thickness of a polysilicon layer used as a gate insulating layer and a gate to decrease. As the polysilicon layer has become thinner, depletion has become more significant. As a result, the dose of an impurity needed to implant into a polysilicon layer to form an n-MOS gate has increased. This increase in dose has presented problems that will be shown by describing a prior art method of fabricating a CMOS transistor.
FIGS. 1 through 5 are cross-sectional views showing a prior art method of fabricating a CMOS transistor.
Referring to FIG. 1, a polysilicon layer 20, which is used as a gate insulating layer (not shown) and a gate, is formed on a semiconductor substrate 10, e.g. a silicon substrate. Next, a buffer oxide 30 is formed on the polysilicon layer 20. The semiconductor substrate 10 includes a p-MOS transistor (TR) region for forming a p-MOS transistor and an n-MOS TR region for forming an n-MOS transistor.
Referring to FIG. 2, a photoresist pattern 40 is formed on the buffer oxide 30. Next, a required dose of impurity, e.g. phosphorous (P), is implanted into the polysilicon layer 20 of the exposed n-MOS TR region using the photoresist pattern 40 as an ion-implantation mask.
If the dose of the impurity implanted into the polysilicon layer 20 of the n-MOS TR region is too large, a damaged region 50 is formed in an upper portion of the polysilicon layer 20 of the n-MOS TR region despite the presence of the buffer oxide 30.
Referring to FIG. 3, the photoresist pattern 40 is removed. Next, the buffer oxide 30 is removed using an oxide etching solution. After the buffer oxide 30 is removed, an antireflection film 60 is deposited on the polysilicon layer 20 using film materials such as silicon-oxy-nitride (SiON). The damaged region 50 remains in the polysilicon layer 20 of the n-MOS TR region.
Referring to FIGS. 4 and 5, after a photoresist pattern (not shown) is formed on the antireflection film 60, etching for gate formation is performed. Thus, a p-MOS transistor gate 20a and an n-MOS transistor gate 20b are formed.
Next, as shown in FIG. 5, the antireflection film 60 is removed by cleaning with a solution including hydrofluoric acid (HF) and hydrogen peroxide (H2O2). However, in this prior art method for fabricating a CMOS transistor, the damaged region 50 of FIG. 5 present in the upper portion of the n-MOS transistor gate 20b is removed during the cleaning. Thus, gate thinning occurs in which the n-MOS transistor gate 20b decreases in height. The height difference between the n-MOS transistor gate 20b and the p-MOS transistor gate 20a can cause a contact failure in a later process.
Embodiments of the invention address these and other limitations in the prior art.